Before we discussed building a driver circuit using discrete components, our focus was primarily on understanding the inner workings of the chip. However, in real-world applications, integrated chips are used much more frequently. High-frequency switching power supplies commonly employ several control methods, including voltage control, current control (which further divides into peak current control and average current control), and phase shift control. Voltage control is straightforward and easy to comprehend, with chips like the TL494 and SG3524 being typical examples. Compared to current control modes, voltage control circuits are simpler, but their response speed is slower. Current control methods, on the other hand, boast faster response times, and chips such as UC3842 and UC3844 are commonly used. Phase-shift control is most often applied in full-bridge soft-switching circuits, with the UCC3895 chip being a popular choice. For more control chip models, you can explore the official websites of companies like Texas Instruments, Semiconductor Components Industries, and Philips.
Today, we will discuss the UC3844, a peak current control chip. It features undervoltage lockout thresholds at 16V (for turn-on) and 10V (for turn-off), making it well-suited for off-line converters with low output. Let's begin by understanding the pin description of the chip, as illustrated in Figure 1:
Taking pin 8 as an example, let’s delve into the internal circuitry of the chip, organizing the circuit modulation process to gain a deeper comprehension and effective usage of the chip, followed by a comparison with other chips.
To grasp the circuit, we first need to understand the internal module composition and analyze its functions. Figure 2 below provides a simplified internal block diagram of the UC3844. Pin 7 serves as the chip’s power supply input. To ensure proper operation of other circuits, the power supply voltage cannot be too low, hence the presence of undervoltage protection. If the power supply voltage is insufficient, the internal circuit cannot output the 5V reference voltage, triggering the undervoltage lockout mechanism, which halts the pulse width modulation output, resulting in a constantly low drive output. Pin 8 outputs a stable 5V reference power supply, which, through an external RC circuit, can generate a frequency-adjustable triangular wave oscillator, serving as one of the inputs for pulse width modulation. Pins 1 and 2 are the output terminal and the negative input terminal of the error amplifier, respectively, providing pulse width modulation based on the voltage feedback signal. Pin 3 is the current sampling input terminal, which also plays a role in pulse width modulation. The pulse width modulation flip-flop is controlled by 6 logic circuits, outputting signals to adjust the duty cycle of subsequent circuits.
After analyzing the internal schematic, we now have a basic understanding of the chip’s functionality. Next, let’s break down the detailed working process. The internal circuit is depicted in Figure 3:
There’s a 36V voltage regulator at the VCC terminal, indicating that the supply voltage can reach up to 36V. However, it cannot be too low. If it is, an undervoltage lockout circuit kicks in. The output passes through a voltage regulator to produce a high-precision 5V voltage. This output is charged and discharged via an RC circuit, generating a triangular wave of a certain frequency. There’s also a positive input terminal that generates a 2.5V input through a precise resistor divider for the error amplifier. The negative input terminal of pin 2 is usually connected to the feedback voltage, amplified by the error amplifier. The pin serves as the output terminal of the amplifier. One purpose of the output is to provide feedback and output compensation. A capacitor is typically connected between the negative input terminal to form an integrator circuit, slowing the voltage and compensating. After passing through two diodes (with approximately a 1.4V voltage drop) and a resistor divider, along with a 1V zener diode in parallel, the input reaches the negative terminal of the current comparator. This indicates that the output Vout can be divided into three stages: (1) less than 1.4V, V_=0V; (2) greater than or equal to 1.4V but less than 4.4V, where V_ is linearly proportional to Vout; (3) greater than 4.4V, V_=1V. The positive input of the current comparator is the current sampling value. When the sampled current feedback voltage exceeds 1V, overcurrent conditions are detected, directly outputting a high level, shutting off the PWM wave (why this happens will be explained later). When the current feedback voltage is less than 1V, it is compared with the output feedback voltage (either from pin 2 or pin 1), and a high level is output as the R terminal of the RS flip-flop. The S-terminal of the RS flip-flop is a pulse waveform derived from the triangular wave after passing through some logic circuits (the rising edge is low, while the discharging process is high, though the exact details of the flip-flop circuit aren’t provided here). The RS flip-flop’s formula is: Qn+1 equals S plus the negation of R ANDed with Qn, then inverted to generate a pulse width modulated wave. The timing process is shown in Figure 4:
The first line represents the capacitor charge and discharge waveform, the second line is the S terminal input waveform, and the third line shows the two input terminals of the current comparator. However, the output compensation curve in the figure is the voltage at pin 1, subtracted by 1.4V, divided by 3, and compared with the current sampling input, forming the fourth line, i.e., the R terminal input. The R and S waveforms are inverted by the RS flip-flop, producing the fifth line, which is the output pulse width modulation waveform. The specific calculations and verification process can be verified independently to deepen understanding. As mentioned earlier, in cases of overcurrent, when the current exceeds the threshold, the current comparator outputs a high level, meaning R=1. From the RS flip-flop formula, we know that Qn+1 equals S, regardless of Qn. Since S and its negation are always 1, the NPN transistor turns on, leading to a constant low output, effectively turning off the MOS transistor.
Figure 5 below illustrates the scenario of a small R and large C. Interested readers should definitely give it a try, clarifying the timing and deepening their understanding.
The explanation about the circuit function is nearly complete. From the analysis, it’s evident that the output duty cycle waveform is related to the peak current of the sample, thus classifying this chip as a peak current control chip. The other voltage output feedback loop can be viewed as the upper limit for comparing the current feedback signal. The voltage feedback loop has a longer response time, but adding an integral compensation capacitor helps reduce errors, stabilizing the duty cycle modulation. The internal structures of these control chips are similar. After mastering the analysis method of the chip, you can attempt to analyze the structure of other control chips to better utilize them in the future.
Also, it has changed again!
The explanation about the circuit function is nearly complete. From the analysis, it’s clear that the output duty cycle waveform is tied to the peak current of the sample, making this chip a peak current control chip. The voltage output feedback loop can be thought of as the upper limit for comparing the current feedback signal. The voltage feedback loop has a longer response time, but adding an integral compensation capacitor reduces errors, stabilizing the duty cycle modulation. The internal structures of these control chips are similar. Once you’ve mastered the analysis method of the chip, you can try analyzing the structure of other control chips to enhance your future usage of them.
Also, it has changed yet again!
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