Before diving into the specifics of building a driver circuit using discrete components, it’s important to understand the inner workings of the chip itself. However, in real-world applications, integrated chips are often preferred due to their simplicity and efficiency. High-frequency switching power supplies commonly employ several control methods, including voltage control, current control (which further divides into peak current control and average current control), and phase shift control. Voltage control is straightforward and easy to grasp, with popular chips like the TL494 and SG3524 being widely used. Compared to current control modes, voltage control circuits are simpler but have slower response times. Current control, on the other hand, boasts faster responses, and typical chips include the UC3842 and UC3844. Phase shift control is frequently applied in full bridge soft switching circuits, such as with the UCC3895 chip. For more models, visit the official websites of companies like Texas Instruments, Semiconductors, and Philips.
Today, we’ll focus on the UC3844, a peak current control chip. This chip features 16V (on) and 10V (off) undervoltage lockout thresholds, making it ideal for low-output offline converters. Let's begin by examining the pin descriptions of the UC3844, as illustrated in Figure 1:
Taking pin 8 as an example, we'll delve into the internal circuitry of the chip, organizing the modulation process to enhance our comprehension and utilization of the chip. We’ll also compare it with other chips.
To understand the circuit, we first need to grasp the internal module composition and analyze its functions. Figure 2 provides a simplified internal block diagram of the UC3844. Pin 7 serves as the chip’s power supply input. To ensure smooth operation of the other circuits, the power supply voltage cannot be too low, thus featuring an undervoltage protection mechanism. If the power supply voltage is insufficient, the internal 5V reference voltage cannot be generated, triggering the undervoltage lockout, which turns off the pulse width modulation output, keeping the drive output low. Pin 8 outputs a stable 5V reference power supply, which, when combined with an external RC circuit, creates a frequency-adjustable triangular wave oscillator. This triangular wave is one of the inputs for pulse width modulation. Pins 1 and 2 serve as the output and negative input terminals of the error amplifier, respectively, feeding back the pulse width modulation as a voltage feedback signal. Pin 3 is the current sampling input terminal, participating in the pulse width modulation process. The pulse width modulation flip-flop is controlled by six logic circuits, determining the duty cycle of subsequent circuits.
After analyzing the internal schematic, we now have a clearer understanding of how each part of the chip operates. Next, let's break down the detailed working process. The internal circuit is shown in Figure 3.
At the VCC terminal, there’s a 36V voltage regulator, indicating that the supply voltage should be no higher than 36V. If the voltage is too low, an undervoltage lockout circuit is activated. The output passes through a voltage regulator to produce a precise 5V voltage. This voltage charges and discharges the RC circuit, generating a triangular wave of a specific frequency. There’s also a positive input terminal that generates a 2.5V input via a precision resistor divider to the error amplifier. The negative input terminal of pin 2 is typically connected to the feedback voltage and amplified by the error amplifier. The output serves as the feedback and output compensation endpoint. A capacitor is usually connected between the negative input terminal to form an integrator circuit, slowing down the voltage change and providing compensation. After passing through two diodes (with approximately a 1.4V voltage drop) and then through a resistor divider with a 1V zener diode, the input reaches the negative terminal of the current comparator. This indicates that the output Vout can be divided into three stages: (1) less than 1.4V, V_=0V; (2) greater than or equal to 1.4V and less than 4.4V, V_ is linearly proportional to Vout; (3) greater than 4.4V, V_=1V. The positive input of the current comparator is the current sampling value. When the sampled current feedback voltage exceeds 1V, overcurrent protection is triggered, directly outputting a high level, turning off the PWM wave (the reason why PWM closes will be explained later). When the current feedback voltage is less than 1V, it is compared with the output feedback voltage (pin 2 or pin 1), outputting a high level as the R terminal of the RS flip-flop. The S terminal of the RS flip-flop is a pulse waveform that becomes a certain frequency after some logic circuits (low level during charging, high level during discharging). The RS flip-flop formula is: Qn+1 equals S plus R not with Qn, then the output is inverted to generate a pulse width modulated wave. The timing process is shown in Figure 4:
The first line is the capacitor charge-discharge waveform, the second line is the S terminal input waveform, and the third line is the two input terminals of the current comparator. However, the output compensation curve in the figure is the voltage at pin 1, after subtracting the 1.4V voltage and dividing it by three to compare with the current sampling input, which is the fourth line, i.e., the R terminal input. The R and S waveforms are inverted by the RS flip-flop output, resulting in the fifth line, the pulse width modulation waveform. The specific calculation and verification process can be verified independently to deepen understanding. As mentioned earlier, in the event of overcurrent, when the current is overcurrent, the current comparator outputs a high level, meaning R=1. From the RS flip-flop formula, it can be deduced that Qn+1 equals S, regardless of Qn, and S is input to the OR gate along with S not. Since S plus S not is always 1, the NPN transistor is turned on when the output is active, resulting in the final output always being low, i.e., the MOS transistor is turned off.
Figure 5 below shows the scenario of a small R and large C. Interested readers must explore it thoroughly to clarify the timing and deepen their understanding.
The explanation about the circuit function is nearly complete here. From the analysis, it can be seen that the output duty cycle waveform is related to the peak current of the sample, making this chip a peak current control chip. The other voltage output feedback loop can be regarded as the upper limit of the comparison of the current feedback signal. The response time of the voltage feedback loop is longer, but adding an integral compensation capacitor reduces errors, similar to the PI algorithm, stabilizing the duty cycle modulation. The internal structures of these control chips are similar. After mastering the analysis method of the chip, one can attempt to analyze the structure of other control chips to better utilize them in the future.
Also, once again, it has evolved!
From the analysis, it is clear that the output duty cycle waveform is related to the peak current of the sample, so this chip is a peak current control chip. The other voltage output feedback loop can be viewed as the upper limit for comparing the current feedback signal. The response time of the voltage feedback loop is longer, but adding an integral compensation capacitor reduces errors, similar to the PI algorithm, stabilizing the duty cycle modulation. The internal structures of these control chips are similar. After mastering the analysis method of the chip, one can attempt to analyze the structure of other control chips to better utilize them in the future.
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