Try to avoid the use of global reset in FPGA development? (3)

Is the timing of the global reset really critical?

The good news is that in most designs (the white paper says it's more than 99.99%? It should be the habit of foreigners writing documents), the timing of the reset signal is irrelevant - usually, most circuits work properly. However, as long as you have encountered a situation where the reset signal is not normal and the circuit does not work properly, then you can say that you are "lucky" to encounter the 0.01% reset signal exception. Figure 4 shows a pipeline reset.

In the pipeline, if the data is processed completely in sequence (ie, there are no feedback, loops, etc.), it is completely irrelevant when the main reset signal is generated. After several cycles of pipeline operation, any abnormal data state will be "rushed out" from the system, which is easy to understand. In fact, in normal pipeline operation, we rarely use the reset operation because it is completely unnecessary. Even in a simulated environment, we tend to configure the initial state in the test program to remove all unknown states from the system, making all inputs in the system valid data.
However, in the case of the one-hot code state machine shown in Fig. 5, the timing of the reset signal does become one of the key factors for the normal operation of the system.

Try to avoid the use of global reset in FPGA development? (3)

Figure 5 Reset of the heat-conditioner state machine
The example of Figure 5 demonstrates a simple reset diagram of a one-hot state machine. The picture clearly shows the potential for a reset failure. If the first trigger containing a one-hot code is released one clock cycle ahead of the second, its own unique heat code will be lost and the entire state machine will always enter an invalid state (cold). The probability of reducing this can often be solved by using a neighboring flip-flop to form a state machine (using a local reset network, the signal is less distorted), but only if the settling time in the timing constraint must be met. In addition, if all flip-flops cannot be released on the active edge of the same clock signal, an already encoded state machine may be tuned into an unknown state, including an illegal state, causing the circuit to fail to operate properly. Therefore, in the circuit designer including the feedback path, the timing requirements of the reset signal need to be carefully considered.
In fact, circuits that do not have a feedback path do not need to use a reset signal at all. For example, in digital signal processing applications, there is no feedback path for the finite impulse response filter (FIR): the filter will only output the sampled value if the valid data fills all beats, otherwise no data is output; therefore, the beat It does not make sense to reset the registers. However, in the finite impulse response filter (IIR), there is a feedback path. If the beat register is reset and an artifact output is generated under an unreliable reset signal, the filter output is significantly affected. In the worst case, the instability caused by the false signal will cause the entire filter to collapse.

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