Once upon a time, engineers using xilinx devices have come into contact with the new term Ultrafastdesign methodology. This term is abbreviated as UFDM, it can be said that Xilinx summarizes a design methodology on all aspects of FPGA design. Many of its contents may have been mentioned in the V6 and V5 generations. For example, the principle of the use of reset signals by xilinx devices was proposed very early. UFDM is a bit similar to the "three represents" we all learned. It organizes the essence and precautions of FPGA design together, as well as a checklist for hardware and software design, which helps engineers more comprehensively reduce debugging time.
UFDM recommends the correct HDL coding style to meet the target device and discuss timing constraints and timing closure. Correct IO constraints, IO pin allocation and layout, physical constraints, and provides techniques to meet timing closure and methods to make FPGA work fast and stable.
In the fields of communication, medical, aviation and consumer electronics, the design of FPGAs has become more and more complex, increasing the capacity of devices and the performance of designs. Under the requirements of TIme to market, the design cycle of many projects is very short. How to achieve the design requirements correctly within a limited time is the key to mass production.
UFDM in Vivado is a collection of the best experience of all engineers using xilinx devices, covering single board design, IP creation, design implementation, timing techniques, hardware debugging and other content. Using UFDM will guide engineers to successfully complete project expectations.
Xilinx recommends that designers use UFDM to read ug949 first. This document contains many PCB design details, FPGA power consumption assessment checks, and DRC check rules. By following the content of the document, you can avoid TIming convergence problems caused by unreasonable layout and save debugging time.
Figure 1. Greaterimpact on QOR
Figure 1 is an FPGA design flow chart. Each FPGA design project is basically a few stages of device selection, IO allocation and PCB layout, RTL implementation, comprehensive layout and routing and timing closure, configuration download and debugging. In the early stage of design, when we use vivado for FPGA design, we have many options, these options can directly affect the performance of the entire design. For example, we can choose to complete the design based on C language, or we can describe the design in HDL language, which will greatly affect the quality of the entire design. Throughout the design process, the vivado UFDM tool is used to continuously generate timing reports and results, and the code of the XDC and source files is continuously revised, which will save a lot of time for layout and wiring later.
The latter stages of the design process have a limited impact on the performance of the entire design, from 100x to 1.1X.
In addition, UFDM also mentioned that the coding needs to match the hardware structure. Many design codes only consider the implementation without considering the bottom layer of the FPGA design, so it is difficult to converge on TIming. Try to use FPGA-specific resources such as BRAM and DSP slices.
I hope that UFDM can help design and become your little assistant!
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