Abstract: Multi-core processors have become the mainstream of processors and have become the mainstream processing platform for various communication and media applications. Communication architecture is one of the core technologies in multi-core systems. The efficiency of inter-core communication is an important indicator affecting the performance of multi-core processors. There are currently three main communication architectures: bus system architecture, crossbar network, and on-chip network. The bus structure design is relatively convenient, the hardware consumption is less, and the cost is lower; the cross switch is a switching network structure suitable for building a large-capacity system; and the on-chip network is a higher-level, larger-scale on-chip network system, which can solve multi-core at present. Architecture issues are one of the most promising solutions for multi-core systems. In the paper, while analyzing the basic principle, system structure and function of the NoC structure, it also provides the design and implementation of some units.
Keywords: multi-core processor; inter-core communication; bus structure; crossbar switch; on-chip network
In the development of the processor, it is more and more difficult to improve the processor's main frequency. It is difficult to see the traditional single processor with the chip main frequency higher than 4 CHz. With Intel and AMD as the representatives, the era of increasing system performance by increasing processor frequency is about to become a thing of the past. There are three reasons for this: Firstly, it is difficult to greatly improve the performance of the CPU by simply raising the frequency of the CPU, thereby slowing down the consumer's enthusiasm for the high-frequency CPU. Secondly, when the CPU clock speed reaches 2 GHz or higher, the processor power consumption also reaches Nearly 100 W, this is the limit of current air-cooling technology; third, in the field of embedded products, the traditional single-core processor structure can not meet the needs of the computing scale of geometric progression. In single-core mode, the development of overall performance is slower and slower with local performance, while thread-level parallel technology based on multi-core provides power for performance improvement. To achieve higher processing performance, multi-core processor architecture emerges at the historic moment. .
A multicore processor is a "execution kernel" with two or more chips in a chip. Multi-core processors face more challenges than single-core processors in the technical research of architecture, such as inter-core communication, memory system, low power, hardware and software coordination. How to achieve mutual cooperation and communication between multi-core cores, to ensure processing speed and improve chip processor performance, is the main content of nuclear communication structure research. In the multi-core communication mode, in addition to continuing to use the bus structure in the single-core SoC, such as AMBA, CoreConnect, Wishbone, OCP, C*BUS, etc., there are mainly crossbar switches (Crossbar Switch), on-chip network (NoC, Network on-Chip). ) and other structures. Among them, the NoC structure is a higher-level and larger-scale on-chip network system, which can solve multi-core architecture problems at present, and is one of the effective solutions for multi-core systems.
1 NoC solves problems and their advantages
As the process progresses, the performance, area, power consumption, and time-to-market limitations of the product make the design and development requirements more and more high. The problems caused by deep sub-micron design make it more difficult to guarantee timing closure in the design. The emergence of NoC (Network on-Chip) has brought continuous development momentum to deep sub-micron SoCs. NoC is a higher-level, larger-scale system-on-a-chip that is an on-chip network system. The core idea of ​​NoC technology is to transplant computer network technology into chip design to solve the multi-CPU architecture problem. Since the network structure is essentially a multi-CPU system, the network-based architecture is one of the most promising solutions for multi-CPU systems. The on-chip network inherits the concept of distributed system and computer network. The interconnect structure has parallel communication between communication modules. The data communication bandwidth is high, the scalability is good, the throughput is large, and the deep/ultra deep can be improved to some extent. The advantages of signal transmission line delay under submicron conditions, it is said that NoC will become the mainstream interconnect structure of the next generation of multicore.
1.1 Problems solved by NoC
The problems solved by NoC are mainly reflected in the reusability of communication modules and the predictability of communication performance.
(1) Increase the reusability of communication modules. In the general SoC concept, reusability is the multiplexing of IP modules. The module-based design approach enhances the reusability of the design, which in turn reduces the gap between manufacturing and design capabilities. The superiority of reusable technology is to build the entire system with a module-based design, reducing the design time for each component to be developed separately, while reducing the possibility of error in human design, thus reducing system design and verification time. However, when the manufacturing process develops below 0.13μm, the interconnect delay between modules becomes a bottleneck that limits the overall performance of the system. The multiplexing of IP modules alone is far from meeting the overall performance requirements. The on-chip network structure is the use of communication components. Reusable technology that connects routing connections between different resource units through regular communication components, providing solutions to problems caused by deep submicron technology.
(2) Enhance the predictability of communication performance. The on-chip network is predictable due to its physical layout and communication network structure. From the perspective of physical performance, the on-chip network structure determines the predictability of the physical properties of the layout. Except for clock and power wiring, the interconnect length and bandwidth between switching units are the same, and the uncertainty and irregularity of the design are limited to the inside of the resource unit, which has no impact on other resource units. And the verification time angle analysis, the module-based reusability of the on-chip network makes the design and verification time predictable. Due to the regularity of the on-chip network structure, the design problem such as task assignment is divided into resource elements, and then the overall application is divided into Independent task. In this way, the design of the network-on-chip system is largely independent of the specific implementation stage, and the modularization is better, which increases the predictability of communication performance.
1.2 Advantages of NoC
The NoC design adopts the global asynchronous local synchronization method to solve the problem of the global synchronization of the whole chip, has good reusability and scalability, and has an average communication bandwidth. In NoC, the communication between the processing core and the network is completed by a simple handshake protocol. Therefore, the electrical parameters and clock signals of the network and each processor can be processed relatively independently and easily controlled. In addition, asynchronous communication can be used between the network and the processor. This eliminates the need for global synchronization of the system clock and avoids the clock and area problems caused by the large clock tree. The large number of local clock lines can greatly reduce the system power consumption.
Each synchronization unit of NoC works together under the premise of complying with the communication protocol. If there is a need for expansion of the NoC system, it is only necessary to add a copy of the communication switch already existing in the system, and at the same time design a communication interface to integrate the extended functional unit. It can be done in the NoC network topology. NoC has a reusable and extensible communication mechanism, and works in the Glo bal Asynohronized Local Synchronized (GALS) mode. There is no global control signal intervention, so the NoC has good scalability.
The primary measure of NoC performance is communication bandwidth. NoC adopts the global asynchronous local synchronization communication method. Although it has some advantages, the disadvantages are also obvious. For example, the real-time communication bandwidth cannot reach the ideal height. However, from the average communication bandwidth of the entire NoC, the global average communication bandwidth is higher than the average communication bandwidth based on the bus method. In summary, with the gradual improvement of process integration, NoC is superior to traditional design methods in solving the global clock synchronization problem, deep submicron effect, scalability and the gap between design and production.
2 NoC topology
The topology is concerned with the layout and interconnection of nodes. The choice of NoC topology has a significant impact on system performance and chip area. NoC can adopt different topologies according to the needs of the application, and can be divided into rule structure and irregular structure. Irregular topology can improve performance, reduce power consumption, and reduce area compared to regular topologies, but at the same time create design issues such as layout design and uneven line length. Topological metrics are usually based on theoretically affecting routing costs and performance, in addition to the number of nodes of interest in the common network, the number of edges, network dimensions, network diameter, average distance, and halving width. Consider the embedded properties of the communication mode, such as message throughput, transmission delay, power consumption, chip and so on.
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