How is an ultra-low-power MCU made?

Low power consumption, high performance, high integration, and low cost have always been the goal pursued by major semiconductor manufacturers, especially smart chips such as microcontrollers (MCUs). Gradually decreasing. But with the "crazy invasion" of the Internet of Things and wearable devices, step-by-step power optimization is no longer a game rule for ultra-low-power MCUs, but a "sudden advance" mode with many indicators related to power consumption (such as ULPBench). The scores are constantly refreshing records, and the record holders can only be "smirking" for months or even days, and they are being contendered by KO.

In general, vendors are focusing on core architecture, multiple operating modes and sleep modes, optimized peripherals such as ADCs, their clocking requirements, and diverse power ranges to reduce power consumption.

This article is based on STMicroelectronics (ST) STM32L4, Atmel SAML21J18A, Texas Instruments SimpleLink C26xx and Cortex-M4F based MSP432, NXP LPC54102 and the unknown Ambiq Micro Apollo in China. Take the series as an example to see how their low power consumption is made!

1. STMicroelectronics STM32L4 Series (STM32L476)

Low-power performance: dynamic operating power as low as 100 μA/MHz; minimum current at 30 nA when off, wake-up time: 5 μs

ULPBench score: 123.5

Core: 80 MHz ARM Cortex-M4 core + DSP + floating point unit (FPU)

CoreMark/MHz: 3.42

Low power reasons: ART accelerator, Flash zero wait execution, dynamic voltage regulation, FlexPowerControl intelligent architecture, 7 power management modes (run, low power operation, sleep, low power sleep, stop 1, stop 2, standby, off ). There is also ST's Batch AcquisiTIon Mode (BAM), which allows for sufficient data exchange with the communication interface in low power mode. FlexPowerControl keeps SRAM standby in low power mode, managing independent power supplies for specific peripherals and I/O.

Working mode power decomposition:

Dynamic operating power consumption: as low as 100 μA/MHz;

Ultra-low power mode: 30 nA has a backup register and does not require a real-time clock (5 wake-up pins);

Ultra low power mode +RTC: 330 nA has a backing register (5 wake-up pins);

Ultra low power mode +32 KB RAM: 360 nA;

Ultra low power mode +32 KB RAM+RTC: 660 nA.

software:

STMicroelectronics provides developers with the STM32 Cube MX Power Simulator to estimate the power of the intended MCU used to execute the code.

ULPBench test environment: STM32 Nucleo

How is an ultra-low-power MCU made?

2.Atmel SAML21 Series (SAML21J18A-UES)

Low power performance: only consumes 35 mA/MHz, only 200 nA in sleep mode

ULPBench score: 185.8

Kernel: ARM Cortex-M0+

Low-power reasons: Five different power ranges use different resources to improve energy efficiency; create an IRQ thread for the CPU and peripherals to implement layered interrupts. Other reasons include the following:

Idle, standby, standby, sleep mode;

Sleepwalking interface

Static and dynamic power gating structures;

Backup battery support;

Two performance levels;

Embedded buck/LDO regulators support real-time dynamic selection;

Low power interface.

ULPBench test environment: SAML21 Xplained Rev2

How is an ultra-low-power MCU made?

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Batch verification artifact: FPGA modern hardware simulation platform, click to download technical white paper

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