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Abstract: In this paper, the design DVR machine as an example, the NIOS embedded workflow, development steps and use soft core.Key words: NIOS; embedded processor; hard disk recording
With the growing maturity of field programmable logic array ( FPGA ) technology, on-chip programmable (SOPC) embedded processors are receiving increasing attention. In particular, Altera's NIOS embedded processor soft core can flexibly implement the functions of embedded processors through software programming methods, and optimize performance for FPGAs, which can greatly improve system performance. In addition, NIOS also has on-chip debugging function, which is convenient for system design and debugging. This paper takes the DVR as an example to study the NIOS control method of external interface devices, including I 2 C interface control, IDE interface control, etc. .
1 Introduction to NIOS development method
The hardware and software development process of NIOS is shown in Figure 1. The specific development steps are described below. The first step in the process is design planning. It needs to divide each software and hardware module according to the system design requirements. The complete NIOS-based SOPC system is a software and hardware composite system, which can be divided into two parts: hardware and software. In the actual design process, you will often encounter such a situation: The required functions can be implemented either in software or pure hardware logic. For example, when an 8-bit 7-segment digital tube display is required in the system, a dynamic scan logic can be designed by the programmable logic in the FPGA to realize the display, or the PIO can be operated by writing a dynamic scan program to complete the above functions. If implemented in hardware, it is obviously necessary to occupy additional hardware resources. However, it is easier to write software and the system speed is not affected. Conversely, software implementation can not increase hardware logic, but dynamic scanning requires CPU processing. Time, which increases the complexity of software writing. The specific method used is related to the system design requirements. Therefore, when designing the plan, it is necessary to determine which functions are implemented in hardware and which functions are implemented in software. When it is usually implemented in software, its design is easy to modify, and it is easier to check errors, and basically does not increase the occupied hardware resources. Therefore, in the design planning, when the required hardware and software costs are equivalent and the performance is guaranteed, the software implementation is given priority.
Once you have determined the partitioning of the hardware and software modules, you can start the specific design process. Usually, the CPU in the embedded system development is unchangeable, so the changes of peripheral devices are also limited by the CPU. Even the hardware of the entire embedded system is fixed and difficult to change (such as the development of PC104). Therefore, in the usual embedded development, more is PCB design and software development. Unlike the usual embedded system development, because NIOS is a flexible and customizable CPU, its peripherals are optional IP cores or custom logic, so you can customize the cutting through the SOPC Builder wizard-based interface according to system design requirements. The appropriate SOPC system. In view of the above characteristics of NIOS development, after the design and planning, the development process of NIOS is divided into two parts: hardware development and software development.
The hardware design flow of NIOS is to customize the appropriate CPU and peripherals, done in SOPC Builder and Quartus II. Here you can flexibly customize the features and even the instructions of the NIOS CPU. You can use the large number of IP Cores provided by Altera to speed up the development of NIOS peripherals and improve the performance of peripherals. At the same time, you can also use a third-party IP Core, or use VHDL, Verilog to customize the peripherals yourself.
After completing the hardware development of NIOS, SOPC Builder can help developers generate the corresponding SDK (software development kit). This is because the system consisting of the NIOS CPU and its peripherals in hardware development is self-customized, and the mapping of memory and peripheral addresses is different. The required SDK should also be proprietary.
SOPC Builder automatically generates the SDK. Based on the generated SDK, developers can enter the software development process. In this part, the embedded system that developers face is customized and tailored, so the hardware limitations will be smaller. Developers can use assembly language, C or C++ language for embedded programming, GNU tools or other third-party tools for program linking and debugging.
2 Designed for NIOS embedded processor of DVR
In the DVR, there are three main parts: image acquisition, image compression, and image storage. Therefore, when designing the external interface, you need to consider the interfaces required for chip control in these three parts.
(1) Image acquisition part. The image acquisition part uses the SAA7113 to complete the acquisition of the video signal. The chip is a programmable video processing chip that uses a CMOS process and can be programmed with a simple I 2 C bus. It unifies the analog signals of different standards into the same digital standard, adopts the ITU-R BT.601 format, encodes the luminance signal and the two color difference signals separately during sampling, uses a single sampling frequency for different standard signals, and any simulation The color subcarrier frequency of the system is independent, so no subcarriers are included in the component system. The sampling frequency is set to 13.5 MHz, which is also the sampling frequency for the luminance signal Y. Since the bandwidth of the chrominance signal is much narrower than the bandwidth of the luminance signal, the sampling rate of the chrominance signals U and V is halved by Y, which is 6.75 MHz. Each digital active line has 720 luma samples and 360 x 2 chroma signal samples. The sampling points of each component are uniformly quantized. An 8-bit PCM encoding is performed for each sample.
(2) Image compression section. The system uses hardware compression to complete JPEG compression of video images. Motion-JPEG (MJPEG) technology is commonly used in video surveillance systems. The MJPEG compression chip compresses the YUV format data input by the A/D conversion chip in MJPEG format. MJPEG consists of JPEG image connections, each with its own quantization table and Huffman code table. MJPEG can compress consecutive tens or even hundreds of frames using only one quantization table and Huffman code table, and only needs to reload the quantization table and Huffman code table when data is lost. This advantage greatly reduces the overhead required for system video decoding. Moreover, MJPEG can be stored in frames, which facilitates the management and playback of data. This system uses Zoran's single-chip MJPEG compression/decompression chip ZR36060 to complete JPEG compression of images.
(3) Image storage section. In order to solve a large number of image data problems, the system uses an IDE (Electronic Integrated Drive) interface hard disk to complete the design. The IDE is intended to refer to a hard drive that integrates a "hard disk controller" with a "disk". This integrated approach reduces the number and length of cables on the hard disk interface, and the reliability of data transmission is enhanced, making it easier to control the hard disk. There are two control modes: PIO mode and DMA mode. This system uses the PIO control method of the IDE hard disk. Because of the NIOS processor, it is not limited to pre-manufactured processor technology, but the processor is customized according to its own standards, and the appropriate peripherals, memories and interfaces are selected as needed. According to the specific requirements of the DVR, the system selects the EP1C6 of Altera's Cyclone series to complete the CPU design; uses the Flash ROM AM29LV065DU to load the program; selects the SRAM as the memory of the CY7C1041CV33 memory; the AS configuration chip of the FPGA is EPCS4.
In the peripheral chip, the video decoding chip SAA7113 requires an I 2 C interface for control. The hard disk that stores images requires an IDE interface, but these interfaces are not available in the NIOS peripheral standard interface. In this case, just set the GPIO interface and use the GPIO interface. Simulate the operation of the I 2 C bus interface and the IDE interface. At the same time, the configuration task of the MJPEG compression chip is also completed by the GPIO interface. Based on the above hardware resource requirements, the module designed by the system inside the FPGA is shown in Figure 2.
The core module of the FPGA internal module is the core of the NIOS processor, followed by Timer 1 and Timer 2, which are used to control the system clock. In order to complete the initial configuration of the SAA7113 and ZR36060, the on-chip ROM is set to store the profile information, and the memory interface and general-purpose I/O interface are completed and the external memory is connected to the I/O device. The entire embedded system is internally connected by modules from the Avalon bus. The debugging of the entire system is done through the JTAG interface and serial port. The debugger is downloaded to the inside of the FPGA through the JTAG interface, and a serial port is used to connect to a display terminal to display debugging information to the PC.
3 control software design
After the system power-on hardware resets, the software automatically sets the controller command codes and their parameters according to the user's needs, thus completing the initialization of the SAA7113, ZR36060, and IDE interfaces, and then controlling the acquisition, compression, and storage of the video signals. The system workflow is shown in Figure 3.
4 overall performance
(1) Recording screen size: 352* 248 or 352* 288. (2) Record or play 25 frames per second, two fields per frame, a total of 50 fields, interlaced. (3) The average size of each picture is 10KB, 0.5MB per second, and 1.8GB per hour. You can connect 10GB to 80GB hard drives as needed to achieve 5 to 40 hours of continuous recording.
5 Conclusion
NIOS is a cost-effective microprocessor soft core that can easily add the interfaces and custom logic that users need to the system. The approach presented in this article reflects the flexibility of the SOPC embedded system. Therefore, this method can effectively shorten the development cycle, and at the same time extend the life cycle of the product, and can continuously upgrade the design based on the original product.
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